The present invention generally relates to high-speed data communications. More specifically, the invention relates to a system and method for supervising signals within a communications system, which solves problems that may be created by a transceiver within the communications system operating in an improper mode.
With the advancement of technology, and the need for instantaneous information, the ability to transfer digital information from one location to another, such as from a central office (CO) to a customer premise (CP), has become more and more important.
A digital subscriber line (DSL) communication system is but one example of a number of communication systems that may simultaneously transmit and receive digital data between two locations. In a DSL communication system, data is transmitted from a CO to a CP via a transmission line, such as a two-wire twisted pair, and is transmitted from the CP to the CO as well, either simultaneously or in different communication sessions. The same transmission line might be utilized for data transfers by both sites or the transmission to and from the CO might occur on two separate lines. Specifically, FIG. 1 illustrates communication between a central office (CO) 10 and a customer premise (CP) 20 by way of twisted-pair telephone line 30. While the CP 20 may be a single dwelling residence, a small business, or other entity, it is generally characterized as having plain old telephone system (POTS) equipment, such as a telephone 22, a public switched telephone network (PSTN) modem 25, a facsimile machine (not shown), etc. The CP 20 may also include a DSL communication device, such as a DSL modem 23 that may permit a computer 24 to communicate with one or more remote networks via the CO 10. When a DSL service is provided, a POTS filter 21 might be interposed between the POTS equipment such as the telephone 22 and the twisted-pair telephone line 30. As is known, the POTS filter 21 includes a low-pass filter having a cut-off frequency of approximately 4 kilohertz to 10 kilohertz, in order to filter high frequency transmissions from the DSL modem 23 and to protect the POTS equipment.
At the CO 10, additional circuitry is provided. Generally, a line card 18 (i.e., Line Card A) containing line interface circuitry is provided for electrically coupling a data transmission to the twisted-pair telephone line 30. In fact, multiple line cards 14, 18 may be provided (two shown for simplicity of installation) to serve a plurality of local loops. In the same way, additional circuit cards are typically provided at the CO 10 to handle different types of services. For example, an integrated services digital network (ISDN) interface card 16, a digital loop carrier line card 19, and other circuit cards supporting similar and other communication services, may be provided.
A digital switch 12 is also provided at the CO 10 and is configured to communicate with each of the various line cards 14, 16, 18, and 19. On the outgoing side of the CO (i.e., the side opposite the various local loops), a plurality of trunk cards 11, 13, and 15 are typically provided. For example, an analog trunk card 11, a digital trunk card 13, and an optical trunk card 15 are illustrated in FIG. 1. Typically, these circuit cards have outgoing lines that support numerous multiplexed DSL service signal transmissions.
Having introduced a conventional DSL communication system 1 as illustrated and described in relation to FIG. 1, reference is now directed to FIG. 2, which is a prior art functional block diagram illustrating the various elements in a DSL communications link 40 between a line card 18 located within a CO 10 and a DSL modem 23 located at a CP 20. In this regard, the DSL communications link 40 of FIG. 2 illustrates transmission of data from a CO 10 to a CP 20 via a twisted-pair telephone transmission line 30 as may be provided by a POTS service provider to complete a designated DSL communications link 40 between a CO 10 and a CP 20. In addition, FIG. 2 further illustrates the transmission of data from the CP 20 to the CO 10 via the same twisted-pair telephone transmission line 30. With regard to the present illustration, data transmissions may be directed from the CP 20 to the CO 10, from the CO 10 to the CP 20 or in both directions simultaneously. Furthermore, data transmissions can flow on the same twisted-pair telephone transmission line 30 in both directions, or alternatively on separate transmission lines (one shown for simplicity of illustration). Each of the separate transmission lines may be designated to carry data transfers in a particular direction either to or from the CP 20.
The CO 10 may include a line card 18 (see FIG. 1) that may comprise a CO-digital signal processor (DSP) 43, a CO-analog front end (AFE) 45, a CO-line driver 47 and a CO-hybrid 49. As illustrated in FIG. 2, the CO-DSP 43 may receive digital information from one or more data sources (not shown) and may send the digital information to a CO-analog front end (AFE) 45. The CO-AFE 45 interposed between the twisted-pair telephone transmission line 30 and the CO-DSP 43 may convert digital data, from the CO-DSP 43, into a continuous time analog signal for transmission to the CP 20 via the one or more twisted-pair telephone transmission lines 30.
One or more analog signal representations of digital data streams supplied by one or more data sources (not shown) may be converted in the CO-AFE 45 and further amplified and processed via a CO-line driver 47 before transmission by a CO-hybrid 49, in accordance with the amount of power required to drive an amplified analog signal through the twisted-pair telephone transmission line 30 to the CP 20.
As further illustrated in FIG. 2, a DSL modem 23 located at a CP 20 may comprise a CP-DSP 42, a CP-AFE 44, a CP-line driver 46, and a CP-hybrid 48. The CP-hybrid 48, located at the CP 20, may de-couple a received signal from the transmitted signal in accordance with the data modulation scheme implemented by the particular DSL data transmission standard in use. The CP-AFE 44, located at the CP 20, having received the de-coupled received signal from the CP-hybrid 48, may then convert the received analog signal into a digital signal, which may then be transmitted to a CP-DSP 42 located at the CP 20. Finally, the digital information may be further transmitted to one or more specified data sources such as the computer 24 (see FIG. 1).
In the opposite data transmission direction, one or more digital data streams supplied by one or more devices in communication with the CP-DSP 42 at the CP 20 may be converted by the CP-AFE 44 and further amplified via the CP-line driver 46. The CP-hybrid 48, located at the CP 20, may then be used to couple the intended analog representations of the various digital signals to a transmit signal in accordance with the data modulation scheme implemented by the particular DSL data transmission standard in use. As will be appreciated by those skilled in the art, the CP-line driver 46 may transmit the various signals with the power required to drive an amplified analog signal through the twisted-pair telephone transmission line 30 to the CO 10. The CP-hybrid 48 enables the DSL modem 23 to simultaneously transmit and receive signals originating from and targeted for the CO 10. The CO-AFE 45 may receive the data from the CO-hybrid 49, located at the CO 10, and may then convert the received analog signal into one or more digital signals, which may then be transmitted to the CO-DSP 43 located at the CO 10. Finally, the digital information may be further distributed to one or more specified data sources (not shown) by the CO-DSP 43.
Having briefly described a DSL communications link 40 between the line card 18 located within the CO 10 and the DSL modem 23 located at the CP 20 as illustrated in FIG. 2, reference is now directed to FIG. 3. In this regard, FIG. 3 is a functional block diagram of the line card 18 of FIGS. 1 and 2 that highlights some of the functional blocks that may comprise the CO-AFE 45 introduced in FIG. 2. As illustrated in FIG. 3, the line card 18 may both send and receive data transmissions from a DSL host 41. In addition, the line card 18 may be configured to communicate with a remote DSL transmission unit at a customer premise 20 (see FIG. 1) via a twisted-pair telephone transmission line 30. The line card 18 may also comprise a CO-DSP 43 and a CO-AFE 45. The CO-AFE 45 may comprise control logic 50, a reference 52, a digital to analog converter (DAC) 54, a CO-line driver 47, a hybrid amplifier 58, and an analog to digital converter (ADC) 56. The control logic 52 may work together with reference 52 in order to coordinate and synchronize data transfers across the CO-AFE 45 in both the transmit and the receive directions.
As illustrated in FIG. 3, a transmit path across the CO-AFE 45 may comprise the DAC 54 and the CO-line driver 47. A receive path across the CO-AFE 45 may comprise the hybrid amplifier 58 and the ADC 56. The CO-AFE 45 interposed between the transmission line 30 and the CO-DSP 43 may convert digital data, from the CO-DSP 43, into a continuous time analog signal for transmission to the CP 20 via one or more transmission lines 30 (one shown). One or more analog signal representations of digital data streams supplied by one or more data sources supplied by the DSL host 41, may be converted in the CO-AFE 45 and further amplified and filtered in the CO-line driver 47 and a line transformer in order to provide a nominal analog signal to a customer premise 20 (see FIGS. 1 and 2).
In the receive direction, the hybrid amplifier 58 may be required to boost the analog signal strength of the received analog signal from the CP 20 (not shown). The received and amplified analog signal from the hybrid amplifier 58 may be forwarded to the ADC 56 which may be configured to convert the received analog signal into one or more digital signals, which may then be transmitted to the CO-DSP 43. Finally, the digital information may be communicated to the DSL host 41, which may further distribute the received data transmissions to one or more specified data sources (not shown).
In communication systems designed to transmit data over metallic transmission lines, the line driver (e.g., the CO-line driver 47) is an amplifier which delivers the energy required to transmit the intended signal to the line via back-matching resistors 59. Often impedance and voltage scaling is performed by coupling the output from the line driver 47 to the transmission line 30 via a transformer 57.
The back-matching resistors 59 serve two purposes. First, the back-matching resistors 59 match the impedance at the end of the transmission line. In order to provide a sufficient return loss, a set of resistors having a resistance approximately equal to the line""s characteristic impedance, scaled by the turns-ratio of the line transformer, should terminate the line. Second, the back-matching resistors 59 permit the line driver 47 to simultaneously receive signals generated from a remote transmitter coupled to the transmission line 30 at the same time the line driver 47 is transmitting. The line driver 47 alone cannot terminate the transmission line 30 because the line driver 47 presents a low impedance to the remotely transmitted signal. The remotely transmitted signal may be recovered by subtracting from the voltage on the transmission line 30 the voltage introduced on the transmission line by the local transceiver.
In CO-DSL modem applications, multiple DSL transceivers may be co-located within the same equipment or even located on the same printed circuit board. Competitive local-exchange carriers (CLECs) often rent equipment space from the various local telephone companies on a volume basis. As a result, DSL transceiver density and power efficiency are important factors for CLECs to consider when entering local DSL service markets. Transceiver density and power efficiency are important to the various telephone companies as well, as higher transceiver density and reduced power requirements directly reduce overhead and operating costs, respectively for the CO operators. In response to transceiver density and power consumption concerns, DSL transceiver designers typically embody each of the functional DSL transceiver blocks in one or more application specific integrated circuits (ASICs).
One problem that arises when a DSL transceiver is integrated on a circuit card such as the line card 18 described hereinabove with regard to FIG. 3 is the possibility of direct current (DC) coupling between the CO-line driver 47 and the transformer 57. Under a condition resulting in a DC flow, the impedance of the transformer 57 may be negligible and as a result the CO-line driver 47 may be shorted through the back-matching resistors 59. Under this condition, the current flowing through the transformer 57 may increase excessively with various negative impacts. By way of example, an excessive DC flow through the transformer 57 may degrade or destroy the transformer windings, may overload a power supply supporting the CO-line driver 47, or may destroy the CO-line driver 47 due to excessive power dissipation.
One method that may be used to prohibit DC flow to the transformer 57 is to add a high-pass filter to the CO-AFE 45. Depending on the architecture of the CO-AFE 45, it is not always possible or desirable to integrate a high-pass filter in the transmit path at a reasonable cost. The introduction of a high-pass filter might lead to a larger circuit package as large integrated capacitors consume significant ASIC silicon area. If the CO-line driver 47 is integrated on an ASIC, the addition of a high-pass filter might necessitate the addition of input and output buffers to drive an external high-pass filter. This would result in less additional silicon area, but would require additional power consumption for the DSL transceiver. Finally, the transformer might be AC coupled to the CO-line driver 47, but this is often cumbersome and expensive due to the excessively large coupling capacitors required due to the low impedance level looking into the line transformer.
A second method that may be used to prohibit DC flow to the transformer 57 is to add DC compensation in the CO-DSP 43. It is possible to include some form of high-pass digital filtering within a DSP. However, implementing a high-pass filter within the CO-DSP 43 presents some danger. If the CO-DSP 43 enters an unexpected operating mode, the state at the output of the CO-line driver 47 is not guaranteed. In addition, if a high-pass filter were added within the CO-DSP 43, it would necessitate accurate measurement of the DC voltage out of the CO-line driver 47 and a feedback line to provide the DC voltage out of the CO-line driver 47 at the CO-DSP 43 to permit the CO-DSP 43 to adjust for the voltage. The high-pass filter approach is complicated and may succeed when the mode of operation is an expected mode and the DC voltage at the output of the CO-line driver 47 is accurately measured. However, if the DSL transmission unit were to encounter an excessively large DC voltage as a result of a CO-DSP 43, CO-AFE 45, or other DSL transmission unit malfunction, the error condition could not be corrected with the CO-DSP 43.
Accordingly, there is a need for a system that can work in concert with a transceiver to prevent possible hardware damaging signal conditions.
In light of the foregoing, the invention is a system and a method for constructing a signal integrity supervisor capable of both detecting and triggering an appropriate response when signals designated for transmission indicate a potential damaging transmitter operating mode. The system and method of the present invention takes advantage of the inherent property of a Delta-Sigma Modulator (DSM) which makes the probability of encountering a long string of consecutive ones or zeroes during nominal operation very small. The signal integrity supervisor ensures nominal transmitter operation by monitoring the data and the clock inputs to a DAC within the transmitter. A signal integrity supervisor system may comprise a data signal supervisor and a clock signal supervisor. A data signal supervisor in accordance with the present invention may comprise a comparator and a maximum value counter. A clock signal supervisor in accordance with the present invention may comprise a pair of monostable circuits, an inverter, and a NAND logic gate. The data signal supervisor may be configured to power down a line driver upon detecting a data stream having a continuous voltage level. The clock signal supervisor may be configured to reset the transmitter if a xe2x80x9cmissingxe2x80x9d clock signal state is detected.
The present invention can also be viewed as providing a method for preventing a transmission unit from forwarding signals that may result in a DC flow condition. In its broadest terms, the method can be described by the following steps: monitoring a data signal; generating a power down signal in response to a data signal of unchanging magnitude; monitoring a clock signal; and generating a reset signal in response to clock signal frequency that fails to meet or exceed a predetermined minimum clock frequency.
Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention, as defined by the claims.